Errata for the book Verilog Designer's Library

• Page 101, the fourth sentence should read "In other words, in a Mealy machine..."

• Page 22, figure 3-6 change signal SIG2a to SIG2d
• Page 23, in the code at the top change "sig2d <= sig;" to "sig2d <= sig2;"
• Page 24, the code to implement the circuit in Figure 3-8 should be:

		assign z = a1 & ~a2;

		always @(posedge clk) begin
			a1 <= a;
			a2 <= a1;
		end

• Page 29, Figure 3-15, output of flip-flop should be labeled Q instead of 1