Errata for the book Designing with FPGAs and CPLDs

• Page 23, change "Designers can bery easily..." to "Designers can very easily..."
• Page 39, figure 3.4 should be labeled "Setup time issues for FPGA inputs" and the second paragraph should read:

  Because of the large routing delays, if an input signal needed to be routed from an input buffer through internal interconnect to a flip-flop in a CLB inside the chip, as shown in Figure 3.4, there would be a large delay, labeled d, from the input pin to the data input of the flip-flop. In order to meet the setup time requirement of the internal flip-flop, labeled h, the setup time requirement for that signal with respect to the clock at the pins of the chip would be the sum of the delay d and setup time h which would be a large number and difficult to meet for devices interfacing with the FPGA. Instead, by placing flip-flops in the I/O blocks, the delay d is very small, resulting in a reasonable setup time at the pins of the chip.

• Page 40, figure 3.5 should be labeled "Setup time issues for FPGA outputs".
• Page 96, figure 5.4 should be the figure below

• Page 100, figure 5.9, the middle AND on the right should be an OR.
• Page 100, figure 5.10, the middle AND on the right should be an OR.
• Page 100, figure 5.9 timing diagram, SEL line should pulse low instead of showing both high and low.
• Page 111 in figure 5.23, the output of bottom flip-flop should be labeled S0.
• Page 127 in the figure in 11 b) there should be a wire from the buffer output.
• Page 127 in the figure in 11 c) there should be a wire from the buffer output.
• Page 127, the diagram in the figure in 11 c) should be the figure below.

• Page 128 in the figure in 13 b) there should be a wire from the buffer output.
• Page 168, Figure 8.1 change "coutners" to "counters".
• Page 207, a better definition of DSP is "A device that manipulates digital representations of analog signals by performing digital processes on them."