Errata for the book Designing with FPGAs and CPLDs.

• Page 23, change "Designers can bery easily..." to "Designers can very easily..."
• Page 96, figure 5.4 should be the figure below

• Page 100, figure 5.9, the middle AND on the right should be an OR.
• Page 100, figure 5.10, the middle AND on the right should be an OR.
• Page 100, figure 5.9 timing diagram, SEL line should pulse low instead of showing both high and low.
• Page 111 in figure 5.23, the output of bottom flip-flop should be labeled S0.
• Page 127 in the figure in 11 b) there should be a wire from the buffer output.
• Page 127 in the figure in 11 c) there should be a wire from the buffer output.
• Page 127, the diagram in the figure in 11 c) should be the figure below.

• Page 128 in the figure in 13 b) there should be a wire from the buffer output.
• Page 168, Figure 8.1 change "coutners" to "counters".